1. Technical Field of the Invention
The present invention relates to a frequency detection circuit. More particularly the invention relates to a frequency detection circuit that detects frequency of an information data signal or a clock signal synchronously recovered with the information data signal, in an optical receiver of an optical transmission system.
2. Description of the Related Art
In recent years, with high-speed and ultra long-distance of long-distance optical communication, an optical direct amplification repeating system has been used where an optical amplified repeater performs optical direct amplification to an optical signal, whose amplitude has been modulated by an information data signal in an optical transmitter, to compensate for attenuation of optical signal amplitude caused by transmission loss of transmission path fiber when the optical signal passes through the transmission path fiber.
In an optical transmission system using such an optical direct amplifier, output light of the optical direct amplifier contains amplified signal light and amplified spontaneous emission (ASE) noise that is noise occurred from the amplifier. A ratio of the ASE noise occupied in the output light of the amplifier increases as the number of repeater sections in multi-repeater transmission becomes larger, or as an input signal power to the optical direct amplifier is low and the amplifier is operated with higher gain.
When an information signal is recovered from the output light, an optical receiver receives an optical signal and the optical signal is converted into an electrical signal by an optical-to-electrical converter. However, probability of erroneous logical judgment of the information signal increases due to jitter in an amplitude direction by the ASE noise and electrical noise, and chromatic dispersion of the transmission path fiber, polarization mode dispersion, jitter in a phase direction caused by an optical-to-electrical amplifier, or the like. For this reason, waveform recovery of an output electrical signal from the optical-to-electrical converter is generally performed by using a Dflip-flop (DFF).
In this case, the DFF converts the electrical signal into a clock signal necessary for retiming, which has synchronized with the electrical signal, and a clock recovery method has been generally used conventionally where clock frequency component is extracted from the information data signal through a narrow band electrical band pass filter and an electrical limiter amplifier or the like amplifies it.
However, because manufacturing difficulties became obvious due to lack of operation speed of the electrical limiter amplifier with higher communication speed, a phase locked loop (PLL) method has been used, where frequency and phase of an output signal of a voltage controlled oscillator (VCO), which performs self-excited oscillation in a signal frequency band, are synchronized with the information data signal and a VCO output signal is thus used as a recovered clock signal, instead of the above-described method.
FIG. 1 is a schematic block diagram of a receiver, in particular, of a high-speed optical transmitter/receiver of the above-described constitution. In FIG. 1, the optical signal transmitted through the transmission path is subject to optical direct amplification by an optical amplifier 14, and then it is input to an optical band pass filter 15 that passes only signal light wavelength and removes the ASE noise light generated by the optical amplifier 14, input to an O/E (optical/electrical) converter 16, and thus becomes the electrical signal. The electrical signal is split into two by a splitter 17, where one is supplied to a DFF 23 for waveform recovery (retiming, reshaping or regeneration) and the other is input to a PLL circuit 18 that recovers a retiming clock signal for the DFF 23.
The PLL circuit 18 is in a well-known constitution, where a phase comparator 19 performs phase comparison to divided output and split output from a frequency divider 22 of a VCO 21 that performs self-excited oscillation in a frequency band of the information data signal, and the compared output becomes a control voltage of the VCO 21 via a loop filter or a low-pass filter 20. The output of the VCO 21 is a recovered clock signal that becomes a clock signal for retiming in the DFF 23.
Then, the information data signal recovered in the DFF 23 is subject to serial/parallel conversion in a demultiplexer (DMUX) 24, and is output after separated into low-speed recovered data and recovered clock signal.
As described, in a method where the PLL circuit is used for clock recovery, it is important to monitor that the output clock signal of the VCO 21 synchronizes with the information data signal in order to make the frequency of the clock signal for retiming match the frequency of the information data signal, and there exists a monitoring method where the frequency of the VCO output clock signal is detected with high accuracy to monitor its frequency shift from the frequency of the information data signal.
Accordingly, the low-speed-recovered clock signal output from the demultiplexer 24 is input to a frequency detection circuit 12 to monitor the relevant clock signal frequency, as shown in FIG. 1. Note that the output of the VCO 21 is split and the frequency of the split output may be monitored. The frequency detection circuit 12 uses, as shown in FIG. 2, a narrow band electrical band pass filter 101 that passes only information data signal frequency and a peak detection circuit 102, and there exists a method where a comparator 103 compares peak detection output with a reference value Vref0 and frequency change of the clock signal is detected as voltage change.
In this method, frequency detection accuracy largely depends on pass band characteristics of the narrow band electrical band pass filter 101 to be used, and the center frequency of the band characteristics is ideally the same as the information data signal frequency (referred to as f0) as shown in FIG. 3. If the frequency characteristics are in a shape that frequencies before and after the center frequency attenuate symmetrically, the frequency shift of ±Δf or more from f0 can be detected by judging the output of the peak detection circuit 102 with a threshold value (Vth: the reference value Vref0 of the comparator 103 in the constitution of FIG. 2).
However, it is extremely difficult to manufacture the filter while its center frequency is accurately matched to f0, and inclinations of the slopes before and after the center frequency f0 are not symmetrical but asymmetrical (different). As a result, the detection circuit can only detect the frequency, where the output voltage of the peak, detection circuit 102 becomes the threshold value Vth or less, in the frequency shift of f0−Δf or less or f0+Δf2 or more (Δf1≠Δf2), and furthermore, it is impossible to freely set the values of Δf1 and Δf2.
Particularly, a CDR (clock and data recovery) circuit, which uses the PLL circuit for recovery of data and clock described above, is used in an optical transmitter/receiver of a SONET (synchronous optical network) system being one of communication methods as well. Further, the output frequency of the VCO in the PLL circuit, which is a clock extraction circuit of the CDR circuit, is required to accurately match receive data in order to conform to a jitter specification in the SONET system.
Now, when it is presumed that the CDR circuit is used in the optical transmission system, the transmission speed of a most general SONET system is about 10 Gbps. Accurately detecting the frequency of such a high-speed clock signal is extremely difficult, because accuracy of the narrow band filter 101 shown in FIG. 2 at the center frequency f0 is low and inclination symmetry of the slopes of the filter transmission band characteristics before and after f0 is poor.